The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
For example, when fabricating field effect transistors (FETs), such as fin-like FETs (FinFETs), flowable chemical vapor deposition (FCVD) processes are frequently used in forming a dielectric material layer over a substrate. A typical FCVD process deposits a dielectric material on the substrate to fill trenches. An annealing process may be used to reduce a wet etch rate of the deposited dielectric material. However, the annealing process might induce undesired dopant diffusion into channel regions (e.g., from a previously doped substrate region), have a negative impact on strained features already existent in the substrate, and/or cause undesired bending of the fin elements. An implantation process may also be used to reduce the wet etch rate of the deposited material. However, such implantation process may induce damage to the fin elements, which may not be fully recovered by a subsequent thermal treatment. In addition, such subsequent thermal treatment may induce defects (e.g., twin defects) in the substrate and fin elements. Thus, existing techniques have not proved entirely satisfactory in all respects.